Why Certified IBM memory?
Check the IBM ServerProven compatibility Web site to ensure that the memory has been tested and certified as being supported for your system. Most third party memory does not meet the stringent performance and quality guidelines required by IBM, and thus is not supported in IBM systems.
Please take note of the following:-
- SDRAM memory in a server can be either registered or unbuffered. The two types cannot be mixed. In registered memory, the registers provide a controlled delay in communication with the chipset. This delay is one clock cycle. This ensures that the clock edge collects all the data, and ensures that the data is accurate and complete in heavily loaded memory systems.
In unbuffered memory, the chipset controller deals directly with the memory. No registers are between the chipset and the memory as they communicate with each other.
- Using incompatible memory is the most common reason memory upgrades do not work. While incompatible memory may work to some extent, it can lead to unpredictable system behavior including data corruption and poor system performance including blue screen stop errors, NMI errors, and intermittent lockups.
- Memory installed after receipt of the system should be verified as fully compatible with the system. It is important to make sure that you are using the correct part numbers when selecting computer memory.
Any third party memory must be a direct replacement for the IBM option part number or replacement (FRU) number.
- When adding memory to a system that uses interleaving, the memory modules must be added in sets of two. Memory interleaving enables memory banks to be accessed simultaneously rather than sequentially. Interleaving can only occur between identical memory modules. Banks of memory are combined and organized into even and odd bytes.
In this arrangement, a data request can be made to one bank, and while that request is pending, a second request can be made to the other bank. Interleaving access to memory increases system performance, because read and write activity occurs nearly simultaneously across multiple memory modules.